In the near future, exascale computing will expect 1000× more memory capacity than available today. However, today's DRAM technology is hitting the wall of energy efficiency and transistor scaling. It is a great challenge to fabricate high density DRAM beyond 22 nm due to difficulties such as efficient charge placement and control of the capacitor, and reliable charge sensing in DRAM. In addition, energy consumption and heat dissipation of DRAM with such a large capacity is a severe issue. In current generation of technology, DRAM power consumption can reach 40% of the server energy consumption. In fact, the idle power consumption of DRAM accounts for more than 40% of the DRAM power usage. In addition, DRAM's leakage of power increases with its capacity and this leakage power can be as much as its dynamic power.
Fortunately, phase-change memory (PCM) has better process scalability and less leakage power. The PCM technology is capable of transforming the Ge2Sb2Te5(GST) material properties to exhibit various resistances in response to heat produced by varying levels of currents. In addition, PCM consumes less leakage current and requires no refresh operations due to its non-volatile property. These attractive properties make the PCM a good alternative to the DRAM for exascale computing in the near future.
However, PCM typically has two major weaknesses: slow write performance and weak write endurance. A PCM chip circuit often limits the maximum instantaneous power due to noise minimization, and hence the number of bits that can be concurrently written is limited to a predefined constant N. Typical value of N is 2, 4, 8 and 16. This constraint limits the number of bytes that can be written to a bank simultaneously, which is referred to as a write unit. Accordingly, writing a cache line of 64 bytes needs multiple serially executed write units, which slows down the overall write performance. Besides slow write, a PCM cell endures around 108-1010 write cycles while a DRAM cell can support over 1015 writes.